1. Field of the Invention
This invention relates to bistable non-volatile semiconductor latches, and, more particularly, to a flip-flop circuit which includes electrically erasable, electrically programmable memory elements for setting and storing the configuration of programmable semiconductor circuitry.
2. Description of the Related Art
There is a strong need to remember the state of conditions entered or derived in semiconductor devices whenever the devices are on. These states must reliably configure the devices to act in one way or another. Examples of devices needing different configurations with the same basic device are EPLD""s (Electrically Programmable Logic Devices), FPGA""s (Field Programmable Gate Arrays) and memory devices that require repairing defective rows or columns of memory cells with spare or redundant rows or columns of memory cells.
Since these devices and systems have no prior knowledge of the desired conditions, non-volatile memory would be needed to store the state of conditions when the devices are turned off. When the devices are turned back on, the state of conditions are restored for proper device operation.
An array of non-volatile memory cells is a way of storing the desired conditions, but because the structure of an array of memory cells requires additional circuitry to function, simultaneous access of all states in the array is not practical. Sometimes in the EPLD case, an array of non-volatile memory cells on- or off-chip is used, and during device and system power-up, the entire content of the array is downloaded into state latches on the device which store and configure the device while it is on. The problem with this scheme is off-chip it requires more system board space and algorithms for downloading the data, and on-chip it requires a memory array with its associated overhead circuitry. Both methods require algorithms for downloading the data into state latches on-chip.
For memory devices, the above scheme is not practical, since on power-up, the memory device needs to start working right away without downloading from a non-volatile memory. Usually, memory devices incorporate fuse links to configure redundant elements and are an efficient way to implement redundancy on a memory device, but this method requires large development and production cost.
A better approach would be integrate a non-volatile latch into the configuration logic of these circuits; however, almost all manufacturable non-volatile memory elements available today require voltages during the erase and write operations that greatly exceed the typical operating voltage range of logic circuitry. In order to accommodate these higher voltages, special high voltage devices and structures must be fabricated in an integrated fashion with the standard logic devices. The additional manufacturing steps require the high voltage devices be integrated, which adds non-productive manufacturing costs to the logic, and increases logic production yield losses. Oftentimes, these two factors increase the cost of the logic well beyond what customers would be willing to accept.
Therefore a need exists to integrate non-volatile memory elements in a way that would eliminate the need for voltages significantly higher that the typical operation voltage range of the logic circuitry.
Therefore, what is needed is a method and apparatus for providing instantaneous logic configuration upon power-up when data latch devices are used to configure the state of the logic without incorporating large numbers of extra devices and manufacturing steps.
It is therefore an object of the invention to provide a semiconductor non-volatile latch which provides non-volatile data storage for logic configurability.
Another object of the invention is to provide a semiconductor non-volatile latch in which the erase operation is enabled with a lower voltage than required heretofore.
It is another object of the invention to provide a semiconductor non-volatile latch in which the write operation is enabled with a lower voltage than required heretofore.
It is still another object of the invention to provide a semiconductor non-volatile latch having an output that can be configured upon power-up or during a recall operation.
Another object of the invention is to provide a semiconductor non-volatile latch which provides full rail CMOS output levels independent of the state of the latch.
It is a further object of the invention to provide a semiconductor non-volatile latch which achieves its operation with a minimum number of additional devices over a standard cross-coupled CMOS inverter latch.
It is yet another object of the invention to provide a semiconductor non-volatile latch which consumes very little power during operation.
Yet another object of the invention is to provide a semiconductor non-volatile latch which eliminates data disturbs of the non-volatile elements during normal operation.
It is still further another object of the invention to provide a semiconductor non-volatile latch which can be produced at lower costs by reliably utilizing a dielectric charge storage.
Yet a further object of the invention is to provide a semiconductor non-volatile latch which can withstand substantial amounts of noise input while the latch is being set upon power-up or during a reset operation.
Still another object of the invention is to provide a semiconductor non-volatile latch whose non-volatile elements can be erased by the application of a negative potential to the gate of the non-volatile elements with respect to the body of the non-volatile elements.
Still yet another object of the invention is to provide a semiconductor non-volatile latch whose non-volatile elements can be programmed by the application of a positive potential to the gate of the non-volatile elements with respect to the body of the non-volatile elements while the logical low levels of the latch are taken to a negative potential.
An additional object of the invention is to provide a semiconductor non-volatile latch whose non-volatile elements can be erased and programmed by using a single negative voltage source in addition to the power supply voltage.
The above and further objects, features and advantages of the invention will become apparent from the detailed description of the preferred embodiments presented hereinafter, when read in conjunction with the accompanying drawings and appended claims.
Thus, according to the invention, there is provided a non-volatile latch, which comprises typically a CMOS latch. The CMOS latch has two CMOS inverters with the output of each CMOS inverter connected, directly or indirectly to the input of the other. Each CMOS inverter has a p-channel IGFET transistor and an n-channel IGFET transistor. The source of the p-channel transistor is connected to a logic high potential and the source and bulk of the n-channel transistor is connected to a controllable signal, Src, the value of which can be set within the range of Vcc to xe2x88x92Vpp, where Vcc, is the supply potential and xe2x88x92Vpp is a negative potential with respect to the supply reference. The gates of each transistor are connected together to form the CMOS inverter input, and the drains of each transistor are connected together to form the CMOS inverter output.
In addition to the CMOS latch, the non-volatile latch has two non-volatile elements, each non-volatile element having at least an n-channel non-volatile memory transistor, each including a source node, a drain node, a gate node, a bulk region, a channel region between the source and drain nodes and lying beneath the gate region, and a charge storage layer residing between, and insulated from, the channel region and the gate region. The gates of the two non-volatile memory transistors are tied together and further to a control gate voltage generator. The bulk of the two non-volatile memory transistors are typically connected together to the controlled signal Src. Either the source or the drain of each of the two non-volatile memory transistors is tied uniquely to one of the drains of the transistors within the CMOS inverters of the CMOS latch.
The remaining non-volatile memory transistor source or drain node is connected to any number or other nodes to form either a static or dynamic current path to the CMOS drains. The current path through the non-volatile elements serves to provide a differential current to the CMOS inverter p-channel drains, especially during the set or reset or recall period when the non-volatile latch output is being set.
The differential current is established by setting the states of the two non-volatile memory transistors to opposite logic conditions, represented by an erased condition or a programmed condition, prior to setting the output of the non-volatile latch.